--
-- CSSE2000 8 Bit Microprocessor
-- Copyright (C) 2011 Nathan Rossi (University of Queensland)
--
-- THIS DESIGN/CODE IS PROVIDED TO YOU UNDER THE FOLLOWING LICENSE:
--
-- All material is restricted to use in the CSSE2000 Project for 2011.
-- You may not redistribute the file/code/design, without the consent of the author.
--
-- DO NOT MODIFY THIS FILE
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;
use work.proc_package.ALL;

entity proc_registers is
	port (
		clk : in std_logic;
		rst : in std_logic;
		en : in std_logic;
		
		-- Port 0
		p_0_wr_en : in std_logic;
		p_0_addr : in PROC_REG_ADDR_TYPE;
		p_0_datain : in PROC_REG_DATA_TYPE;
		p_0_dataout : out PROC_REG_DATA_TYPE;
		
		-- Port 1
		p_1_addr : in PROC_REG_ADDR_TYPE;
		p_1_dataout : out PROC_REG_DATA_TYPE
	);
end proc_registers;

architecture Behavioral of proc_registers is
	-- Number of Registers
	constant NUM_REGS : integer := 16;

	-- Register Array Type
	type REGISTER_FILE_TYPE is array (0 to NUM_REGS-1) of PROC_REG_DATA_TYPE;
	-- Register Array Signal
	signal register_file : REGISTER_FILE_TYPE := (others => (others => '0'));
begin

	-- Writes are synchronous (Async Reset)
	process (clk)
	begin
		if rising_edge(clk) then
			if (rst = '1') then
				register_file <= (others => (others => '0'));
				p_0_dataout <= (others => '0');
				p_1_dataout <= (others => '0');
			elsif (en = '1') then
				if (p_0_wr_en = '1') then
					-- Port 0 write
					register_file(conv_integer(p_0_addr)) <= p_0_datain;
				end if;
				
				-- Read Outputs are Buffered. (Read First Mode)
				p_0_dataout <= register_file(conv_integer(p_0_addr));
				p_1_dataout <= register_file(conv_integer(p_1_addr));
			end if;
		end if;
	end process;

end Behavioral;

